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4.5 ghz ultrahigh dynamic range, dual differential amplifier data sheet ADL5566 rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. tradema rks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2012C 2013 analog devices, inc. all rights reserved. technical support www.analog.com features ? 3 db bandwidth of 4.5 ghz (a v = 16 db) fixed 16 d b gain channel - to - channel g ain e rror : 0.1 db at 100 mhz channel - to - channel p hase e rror : 0.06 at 100 mhz differential or single - ended input to differential output i/o dc - coupled or ac - coupled low noise input stage: 1. 3 nv/hz rti at a v = 16 db low broadband distortion (a v = 16 db) , s upply = 5 v 1 0 mhz: ? 1 03 dbc (hd2), ?10 7 dbc (hd3) 100 mhz: ? 9 5 dbc (hd2), ? 100 dbc (hd3) 200 mhz: ? 94.5 dbc (hd2), ?8 7 dbc (hd3) 500 mhz: ? 83 dbc (hd2), ?6 4 dbc (hd3 ) imd3 of ? 95 dbc at 2 00 mhz center maintains low single - ended distortion performance out to 500 mhz slew rate: 1 6 v/ns maint ains low distortion down to 1.2 v vcom fixed 16 db gain can be reduced by adding external resistors fast settling and overdrive re covery of 2 .5 ns single - supply operation: 2.8 v to 5.2 v power - down low dc power consumption, 462 mw at 3.3 v supply applications differential adc drivers single - ended - to - differential conversion rf/if gain blocks saw filter interfacing functional block diagram vcom1 r f r f r g r g vcc1/vcc2 vin1 vip1 enbl1 von1 vop1 vcom2 r f r f r g r g vin2 gnd enbl2 vip2 von2 vop2 ADL5566 10916-001 figure 1 . general description the ADL5566 is a high performance , dual differential amplifier optimized for if and dc applications. the amplifier offers low noise of 1.3 nv/hz and excellent distortion performance over a wide frequency range , making it an ideal driver for high speed 16- bit analog - to - digital converters (adcs) . t he ADL5566 is ideally s uited for use in high performance , zero if/complex if receiver designs. in addition , this device has excellent low dist ortion for single - ended input drive applications. the ADL5566 provides a ga in of 16 db. for the single - ended input configur ation, the gain is reduced to 14 db. using two external series resistors for each amplifier expand s the gain flexibility of the amplifier and allows for any gain selection from 0 db to 16 db for a differentia l input and 0 db to 1 4 db for a single - ended input . in addition, this device maintain s low distortion down to output (vocm) levels of 1.2 v providing an added capability for driving cmos ad c s at ac levels up to 2 v p - p . the quiescent current of the ADL5566 , using a 3.3 v supply , is typically 7 0 ma per amplifier . w hen disabled, it consumes less than 3.5 ma per amplifier and has ?25 db of input - to - output isolation at 100 mhz. the device is optimized for wideband, low distortion, and noise performance, giving it unprecedented performance for overall spurious - free dynamic range (sfdr) . these attributes, together with its adjustable gain capability, make this device the amplifier of choice for driving a wide variety of adcs, mixers, pin diode attenuators, saw filters, and multi - element discrete devices. fabricated on an analog devices, inc., high speed sige process, the ADL5566 is supplied in a compact 4 mm 4 mm, 24 - lead lfcsp package and operates over the ? 40 c to +85c temperature range.
ADL5566 data sheet rev. a | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 6 thermal resistance ...................................................................... 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 circuit description ......................................................................... 14 applications information .............................................................. 15 basic connections ...................................................................... 15 input and output interfacing ................................................... 16 gain adjustment and interfacing ............................................ 16 adc interfacing ......................................................................... 18 dc - coupled receiver application .......................................... 19 layout considerations ............................................................... 20 soldering information and recommended land pattern .... 21 evaluation board ........................................................................ 21 outline dimensions ....................................................................... 24 ordering guide .......................................................................... 24 revision history 12/13 rev. 0 to rev. a changes to enbl1/enbl2 threshold parameter , table 1 ......... 3 change to table 2 ............................................................................. 6 11 /12 revision 0: initial version
data sheet ADL5566 rev. a | page 3 of 24 specificat ions v s = 3.3 v, v cm = 1.65 v, v s = 5 v, v cm = 2.5 v, r l = 200 ? differential, a v = 1 6 db, c l = 1 pf differential, f = 1 0 0 mhz, t a = 25c , parameters specified as ac - coupled differential input and differential output, unless otherwise noted. table 1. test conditions/ 3.3 v 5 v parameter comments min typ max min typ max unit dynamic performance ?3 db bandwidth a v = 16 db, v out 0.5 v p - p 4500 4500 mhz bandwidth 0.1 db flatness v out 1.0 v p -p 500 500 mhz gain accuracy 1 1 db gain error 1000 mhz, channel a to channel b 0.02 0.02 db phase error 1000 mhz, channel a to channel b 0.5 0.5 degrees gain supply sensitivity v s 5% 3.4 5.6 mdb/v gain temperature sensitivity ?40c to +85c 0 .5 0.5 mdb/c slew rate rise, a v = 16 db, r l = 200 ?, v out = 2 v step 16 18 v/ns fall, a v = 16 db, r l = 200 ?, v out = 2 v step 18 20 v/ns settling time 2 v step to 1% 890 750 ps overdrive recovery time v in = 4 v to 0 v step, v out 10 mv 2.5 2.5 ns reverse isolation (s12) 75 75 db channel isolation channel a -to - channel b a v = 16 db 82.5 82.5 db input/output characteristics input common - mode range 1.2 1.8 1.3 3.5 v input resistance (differential) a v = 16 db 160 160 ? input resistance (single - ended) a v = 14 db 150 150 ? input capacitance (single - ended) 1.1 1.1 pf input bias current 5 5 a cmrr 44 44 db output common - mode range 1.25 1.8 1.25 3 v output common - mode offset ref erenced to vcc/2 ?100 +20 ?100 +20 mv output common - mode drift ?40c to +85c 2 3.5 mv/c output differential offset voltage ?20 +20 ?20 +20 mv output differential offset drift ?40c to +85c 1.1 1.7 mv/c output resistance (differential) 11 11 ? maximum output voltage swing 1 db compressed 3.4 5 v p -p power interface supply voltage 2.8 3.3 5.2 2.8 5 5.2 v enbl1/enbl2 threshold device disabled, enbl low 0.5 0.6 v device enabled, enbl high 1.5 1.5 v enbl1/en bl2 input bias current enbl high 500 500 na enbl low ?165 ?165 a quiescent current enbl high 140 150 160 175 ma enbl low 7 9 ma
ADL5566 data sheet rev. a | page 4 of 24 test conditions/ 3.3 v 5 v parameter comments min typ max min typ max unit noise/harmonic performance 10 mhz second/third harmonic distortion (hd2/hd3) a v = 16 db, r l = 200 ?, v out = 2 v p -p ?99.1/?111 ?103.1/?107.3 dbc output ip3/third - order intermodulation distortion (oip3/imd3) a v = 16 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) +50.2/?103.3 +49.4/?101.8 dbm/dbc output ip2 second - order intermodulation distortion (oip2/imd2) a v = 16 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) + 90.8/?92.1 + 91.2/?92.5 dbm/dbc 1 db compression point, rto (op1db) a v = 16 db 14 17.7 dbm noise spectral density, rti (nsd) a v = 16 db 1.28 1.32 nv/hz noise figure (nf) a v = 16 db 6.47 6.66 db 100 mhz second/third harmonic distortion (hd2/hd3) a v = 16 db, r l = 200 ?, v out = 2 v p -p ?89/?92.1 ?94.7/?100 dbc output ip3/third - order intermodulation distortion (oip3/ imd3) a v = 16 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) +49.4/?101.9 +50.9/?104.7 dbm/dbc output ip2 second - order intermodulation distortion (oip2/imd2) a v = 16 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) +96.9/ ? 98.2 +98.9/ ? 100.2 dbm/dbc 1 db compression point, rto (op1db) a v = 16 db 14.2 17.8 dbm noise spectral density, rti (nsd) a v = 16 db 1.26 1.3 nv/hz noise figure (nf) a v = 16 db 6.36 6.58 db 200 mhz second/third harmonic distortio n (hd2/hd3) a v = 16 db, r l = 200 ?, v out = 2 v p -p ?92.7/?80.2 ?94.5/?87.2 dbc output ip3/third - order intermodulation distortion (oip3/imd3) a v = 16 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) +45.9/?94.7 +46/?95 dbm/dbc output ip2 second - order intermodulation distortion (oip2/imd2) a v = 16 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) +80.4/?81.7 +82.6/ ? 83.9 dbm/dbc 1 db compression point, rto (op1db) a v = 16 db 14.1 17.7 dbm noise spectral density, rt i (nsd) a v = 16 db 1.25 1.28 nv/hz noise figure (nf) a v = 16 db 6.31 6.48 db 500 mhz second/third harmonic distortion (hd2/hd3) a v = 16 db, r l = 200 ?, v out = 2 v p -p ?82.6/?60.5 ?82.8/?64.2 dbc output ip3/third - order intermodul ation distortion (oip3/imd3) a v = 16 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) +30.7/?64.7 +32.4/?67.8 dbm/dbc output ip2 second - order intermodulation distortion (oip2/imd2) a v = 16 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) +74.2/ ? 75.5 +75.8/ ? 77.1 dbm/dbc noise spectral density, rti (nsd) a v = 16 db 1.32 1.35 nv/hz noise figure (nf) a v = 16 db 6.64 6.83 db
data sheet ADL5566 rev. a | page 5 of 24 test conditions/ 3.3 v 5 v parameter comments min typ max min typ max unit 1000 mhz second/third harmonic distortion (hd2/hd3) a v = 16 db, r l = 200 ?, v out = 2 v p -p ?57.6/?43 ?57.1/?45.9 dbc output ip3/third - order intermodulation distortion (oip3/imd3) a v = 16 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) +23.2/?49.4 +24.8/?52.6 dbm/dbc output ip2 second - order intermodulation distort ion (oip2/imd2) a v = 16 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) +56.1/?57.4 +55.9/?57.2 dbm/dbc noise spectral density, rti (nsd) a v = 16 db 1.93 1.99 nv/hz noise figure (nf) a v = 16 db 9.45 9.66 db
ADL5566 data sheet rev. a | page 6 of 24 absolute maximum r atings table 2. parameter rating output voltage swing bandwidth product 2300 v p -p mhz supply voltage , v cc 5.25 v vip x , vin x v cc + 0.5 v i out max imum 30 ma internal power dissipation 900 mw maximum junction temperature 13 5c operating temperature range ?40c to +10 5c storage temperature range ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditio ns above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance table 3 lists the ju nction - to - air thermal resis tance ( ja ) and the junction - to - paddle thermal resistance ( jc ) for the adl556 6 . table 3 . thermal resistance package type ja 1 jc 2 unit 24- lead lfcsp 34.0 1.8 c/w 1 me asured on analog devices evaluation board. for more information about board layout, see the pattern section . 2 based on simulation with jedec standard jesd51. esd caution
data sheet ADL5566 rev. a | page 7 of 2 4 pin configuration an d function descripti ons vip1 nc nc vip2 vin2 von2 vop2 nc nc vop1 von1 vin1 enbl2 vcom2 vcc2 nc nc nc vcom1 vcc1 enbl1 nc nc nc 2 1 3 4 5 6 18 17 16 15 14 13 8 9 10 1 1 7 12 20 19 21 22 23 24 ADL5566 t o p view 1. nc = no connect. do not connect to this pin. 2. the exposed paddle is internally connected to gnd and must be soldered to a low impedance ground plane. 10916-002 figure 2 . pin configuration table 4 . pin function descriptions pin o. nemonic description 1 vin1 balanced differential input for a mplifier 1. biased to v cc /2 , typically ac - coupled. input for a v = 16 db. 2 vip1 balanced differentia l input for a mplifier 1. biased to v cc /2 , typically ac - coupled. input for a v = 16 db. 3, 4, 7, 8, 12, 15, 16, 19, 23, 24 nc no connect. do not connect to this pin. solder to ground. 5 vip2 balanced differential input for a mplifier 2. biased to v cc /2 , typ ically ac - coupled. input for a v = 16 db. 6 vin2 balanced differential input for a mplifier 2. biased to v cc /2 , typically ac - coupled. input for a v = 16 db. 9 enbl 2 enable for a mplifier 2. apply positive voltage (1.3 v < enbl2 < vcc 2 ) to activate device . 10 vcom2 common - mode voltage. a voltage applied to this pin sets the common- mode voltage of the inputs and output s of a mplifier 2. if left open , vcom2 = v cc /2 . typically , it is decoupled to ground with a 0.1 f capacitor. 11 vcc 2 positive s upply for a mpl ifier 2. 13 von2 balanced differential output for a mplifier 2. biased to v c c / 2 , typically ac - coupled. 14 vop2 balanced differential output for a mplifier 2. biased to v cc /2 , typically ac - coupled. 17 vop1 balanced differential output for a mplifier 1 . bias ed to v cc /2 , typically ac - coupled. 18 von1 balanced differential output for a mplifier 1 . biased to v cc /2 , typically ac - coupled. 20 vcc 1 positive s upply for a mplifier 1. 21 vcom1 common - mode voltage. a voltage applied to this pin sets the common- mode vol tage of the inputs and output s of a mplifier 1. if left open , vcom1 = v cc /2. typically , it is decoupled to ground with a 0.1 f capacitor. 22 enbl 1 enable for a mplifier 1. apply positive voltage (1.3 v < enbl 1 < vcc 1 ) to activate device . ep the e xposed pad dle is internally connected to gnd and must be soldered to a low impedance ground plane.
ADL5566 data sheet rev. a | page 8 of 24 typical performance characteristics v s = 3.3 v, v cm = 1.65 v, r l = 200 ? differential, a v = 1 6 db, c l = 1 pf differential, f = 1 0 0 mhz, t a = 25c , parameters spec ified as ac - coupled differential input and differential output, unless otherwise noted. ?15 ?10 ?5 0 5 10 15 20 25 10m 100m 1g gain (db) frequenc y (hz) 3.3v, 25c 5v, 25c 10916-003 figure 3 . gain vs. frequency response for 200 ? differential load, v pos = 3.3 v and v pos = 5 v, 25c ?15 ?10 ?5 0 5 10 15 20 25 10m 100m 1g gain (db) frequenc y (hz) 3.3v, ?40c 3.3v, +25c 3.3v, +85c 3.3v, +105c 10916-004 figure 4 . gain vs. frequency response for 200 ? differential load, four temperatures, v pos = 3.3 v 10m 100m 1g frequenc y (hz) ?15 ?10 ?5 0 5 10 15 20 25 gain (db) 5v, ?40c 5v, +25c 5v, +85c 5v, +105c 10916-005 figure 5 . gain vs. frequency response for 200 ? differential load, four temperatures, v pos = 5 v 10916-106 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 10 100 1000 gain error (db) phase error (degrees) frequenc y (mhz) sdd21 phase sdd21 mag figure 6 . channel - to - channel gain error and phase error vs. frequency 0 5 10 15 20 25 0 50 100 150 200 250 op1db (dbm) frequenc y (mhz) 5v, +2 5 c 5v, ?4 0 c 5v, +8 5 c 5v, +10 5 c 3.3v, +2 5 c 3.3v, ?4 0 c 3.3v, +8 5 c 3.3v, +10 5 c 10916-006 figure 7 . op1db vs. frequency for 200 ? differential load, four temperatures, v pos = 3.3 v , v pos = 5 v 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10m 100m 1g noise figure (db) frequenc y (hz) 3.3v supply 5v supply 10916-007 figure 8 . noise figure vs. f requency at v pos = 3.3 v , v pos = 5 v , 25c
data sheet ADL5566 rev. a | page 9 of 24 10m 100m 1g frequency (hz) 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 noise spectral density (nv/ hz) 3.3v supply 5v supply 10916-008 figure 9. noise spectral density vs. frequency at v pos = 3.3 v and v pos = 5 v 0 10 20 30 40 50 60 0 100 200 300 400 500 600 700 800 900 1000 oip3 (dbm) frequency (mhz) oip3, 3.3v, 25c, 2v p-p oip3, 5v, 25c, 2v p-p oip3, 3.3v, 25c, 1v p-p oip3, 5v, 25c, 1v p-p 10916-009 figure 10. output third-order intercep t (oip3) at output level at 2 v p-p composite, r l = 200 , v pos = 3.3 v and v pos = 5 v 0 10 20 30 40 50 60 0 100 200 300 400 500 600 700 800 900 1000 oip3 (dbm) frequency (mhz) oip3, 3.3v, +25c, 2v p-p oip3, 5v, +25c, 2v p-p oip3, 3.3v, +85c, 2v p-p oip3, 5v, +85c, 2v p-p oip3, 3.3v, ?40c, 2v p-p oip3, 5v, ?40c, 2v p-p oip3, 3.3v, +105c, 2v p-p oip3, 5v, +105c, 2v p-p oip3, 3.3v, +25c, 1v p-p oip3, 5v, +25c, 1v p-p oip3, 3.3v, +85c, 1v p-p oip3, 5v, +85c, 1v p-p oip3, 3.3v, ?40c, 1v p-p oip3, 5v, ?40c, 1v p-p oip3, 3.3v, +105c, 1v p-p oip3, 5v, +105c, 1v p-p 10916-010 figure 11. output third-order intercept (oip3) vs. frequency, overtemperature, output le vel at 2 v p-p composite, r l = 200 , v pos = 3.3 v and v pos = 5 v 0 10 20 30 40 50 60 ?6?5?4?3?2?1012345678910 oip3 (dbm) p out /tone (dbm) oip3, 5v, 25c oip3, 3.3v, 25c 10916-011 figure 12. output third-order intercept (oip3) vs. output power (p out ) per tone, frequency 200 mhz, v pos = 3.3 v and v pos = 5 v ?120 ?100 ?80 ?60 ?40 ?20 0 0 100 200 300 400 500 600 700 800 900 1000 imd3 (dbm) frequency (mhz) imd3, 3.3v, +25c, 2v p-p imd3, 5v, +25c, 2v p-p imd3, 3.3v, +85c, 2v p-p imd3,5v, +85c, 2v p-p imd3, 3.3v, ?40c, 2v p-p imd3, 5v, ?40c, 2v p-p imd3, 3.3v, +105c, 2v p-p imd3, 5v, +105c, 2v p-p imd3, 3.3v, +25c, 1v p-p imd3, 5v, +25c, 1v p-p imd3, 3.3v, +85c, 1v p-p imd3, 5v, +85c, 1v p-p imd3, 3.3v, ?40c, 1v p-p imd3, 5v, ?40c, 1v p-p imd3, 3.3v, +105c, 1v p-p imd3, 5v, +105c, 1v p-p 10916-012 figure 13. imd3 vs. frequency, over temperature, output level at 2 v p-p composite, r l = 200 , v pos = 3.3 v and v pos = 5 v ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ? 20 0.5 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 vcom (v) imd3 (dbc) 5v supply 3.3v supply 10916-017 figure 14. imd3 vs. vcom, output level at 2 v p-p composite, r l = 200 , v pos = 3.3 v and v pos = 5 v, frequency = 100 mhz
ADL5566 data sheet rev. a | page 10 of 24 ?120 ?115 ?110 ?105 ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ? 50 0 50 100 150 200 250 300 350 400 450 500 frequency (mhz) imd3 (dbc) imd3 100 ? load imd3 150 ? load imd3 200 ? load 10916-031 figure 15. imd3 vs. frequency, r l = 100 , r l = 150 , and r l = 200 , v pos = 3.3 v, input common mode = 1.65 v, output common mode = 1.25 v, v out = 1.5 v p-p 20 25 30 35 40 45 50 55 60 0 50 100 150 200 250 300 350 400 450 500 frequency (mhz) oip3 (dbm) 10916-032 figure 16. single-ended oip3 vs. frequency, v pos = 3.3 v, 2 v p-p composite output, r l = 200 10916-053 ?120 ?100 ?80 ?60 ?40 ?20 0 0 20 40 60 80 100 120 0 100 200 300 400 500 600 700 800 900 1000 imd2 (dbc) oip2 (dbm) frequency (mhz) 3.3v oip2 5v oip2 3.3v imd2 5v imd2 figure 17. oip2/imd2 vs. frequency ?160 ?140 ?120 ?100 ?80 ?60 ? 40 ?120 ?100 ?80 ?60 ?40 ?20 0 0 100 200 300 400 500 600 700 800 900 1000 hd3 (dbc) hd2 (dbc) frequency (mhz) hd3, 5v, 25c, 1v p-p hd3, 3.3v, 25c, 2v p-p hd3, 5v, 25c, 2v p-p hd3, 3.3v, 25c, 1v p-p hd2, 3.3v, 25c, 2v p-p hd2, 5v, 25c, 2v p-p hd2, 3.3v, 25c, 1v p-p hd2, 5v, 25c, 1v p-p 10916-013 figure 18. harmonic distortion (hd2/hd3) vs. frequency, output level at 2 v p-p composite, r l = 200 , v pos = 3.3 v and v pos = 5 v ?160 ?140 ?120 ?100 ?80 ?60 ? 40 ?120 ?100 ?80 ?60 ?40 ?20 0 0 50 100 150 200 250 300 350 400 450 500 hd3 (dbc) hd2 (dbc) frequency (mhz) hd2, 3.3v, +25c hd2, 3.3v, +85c hd2, 3.3v, ?40c hd2, 3.3v, +105c hd2, 5v, +25c hd2, 5v, +85c hd2, 5v, ?40c hd2, 5v, +105c hd3, 3.3v, +25c hd3, 3.3v, +85c hd3, 3.3v, ?40c hd3, 3.3v, +105c hd3, 5v, +25c hd3, 5v, +85c hd3, 5v, ?40c hd3, 5v, +105c 10916-014 figure 19. harmonic distortion (hd2/hd3) vs. frequency, output level at 2 v p-p composite, r l = 200 , v pos = 3.3 v and v pos = 5 v ?120 ?100 ?80 ?60 ?40 ?20 0 ?180 ?160 ?140 ?120 ?100 ?80 ? 60 ?20246810 hd3 (dbc) hd2 (dbc) p out /tone (dbm) 3.3v, hd3, 25c 5v, hd3, 25c 3.3v, hd2, 25c 5v, hd2, 25c 10916-015 figure 20. harmonic distortion (hd2/hd3) vs. output power (p out ) per tone, frequency = 200 mhz, r l = 200 , v pos = 3.3 v and v pos = 5 v
data sheet ADL5566 rev. a | page 11 of 24 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0.51.01.52.02.53.0 vcom (v) hd2 and hd3 (dbc) hd2, 3.3v hd3, 3.3v hd2, 5v hd3, 5v 10916-016 figure 21. harmonic distortion (hd2 /hd3) vs. vcom, output level at 2 v p-p, r l = 200 , v pos = 3.3 v and v pos = 5 v, frequency = 100 mhz ?120 ?115 ?110 ?105 ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ? 50 0 50 100 150 200 250 300 350 400 450 500 frequency (mhz) hd2 (dbc) 10916-029 hd2 100 ? load hd2 200 ? load figure 22. hd2 vs. frequency, r l = 100 and r l = 200 , v pos = 3.3 v, input common mode = 1.65 v, output common mode = 1.25 v, v out = 1.5 v p-p ?120 ?115 ?110 ?105 ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ? 50 0 50 100 150 200 250 300 350 400 450 500 frequency (mhz) hd3 (dbc) hd3 200 ? load hd3 100 ? load 10916-030 figure 23. hd3 vs. frequency, r l = 100 and r l = 200 , v pos = 3.3 v, input common mode = 1.65 v, output common mode = 1.25 v, v out = 1.5 v p-p ?110 ?105 ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ? 60 0 100 200 300 400 500 frequency (mhz) harmonic distortion (dbc) hd2 at 3.3v hd3 at 3.3v hd2 at 5.0v hd3 at 5.0v 10916-033 figure 24. single-ended harmonic distortion (hd2/hd3) vs. frequency, v pos = 3.3 v and v pos = 5 v, v out = 2 v p-p, r l = 200 ?120 ?115 ?110 ?105 ?100 ?95 ?90 ?85 ? 80 0123456 distortion product (dbc) frequency (mhz) hd2 imd3 hd3 10916-019 figure 25. low frequency distortion (hd2/hd3/imd3) vs. frequency, output level at 2 v p-p, r l = 200 , v pos = 3.3 v ch2 100mv/div a ch3 1.1v 50 ? 8g 8g b w ch3 500mv/div 50 ? b w 3 2 10916-020 figure 26. enblx time domain response, v pos = 3.3 v
ADL5566 data sheet rev. a | page 12 of 24 ch1 400mv 2ns a ch1 0v 1 10916-021 figure 27 . large signal pulse response u sing a slow transient signal generator , 4 v p - p , v pos = 3.3 v 0 5 10 15 20 25 30 35 40 45 50 55 60 10 100 1000 cmrr (db) frequenc y (mhz) 10916-022 figure 28 . common - mode rejection ratio (cmrr) vs. frequency 0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000 grou p del a y (ps) frequenc y (mhz) 10916-023 figure 29 . group delay vs. frequency frequenc y (mhz) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 100 1000 reverse isolation (db) 10916-024 figure 30 . reverse isolation (s12) vs. frequency 10 100 1000 frequenc y (mhz) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 120 130 140 150 160 170 180 190 200 210 220 equivalent parallel input cpapcitance (pf) equi v alent series input resis t ance (?) resitance capacitance 10916-025 figure 31 . s11 equivalent rlc parallel network 10 100 1000 frequenc y (mhz) 0 1 2 3 4 5 6 7 8 9 10 0 2 4 6 8 10 12 14 16 18 20 equivalent series output inductance (nh) equivalent series output resistance (?) resistance capacitance 10916-026 figure 32 . s22 equivalent rlc parallel network
data sheet ADL5566 rev . a | page 13 of 24 ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 10m 100m 1g 10g frequenc y (hz) cross t alk (db) 10916-028 figure 33 . output referred crosstalk, channel a to channel b, v pos = 3 .3 v, vcom = 1.65 v 60 65 70 75 80 85 ?40 ?20 0 20 40 60 80 100 i supply (ma) temper a ture (c) 5v 3.3v 09959-027 figure 34 . i supply vs. temperature, r l = 200 ?, v pos = 3.3 v and v pos = 5 v
ADL5566 data sheet rev. a | page 14 of 24 circuit description the ADL5566 is a high gain, fully differential dual amplifier/adc driver that uses a 2.8 v to 5 v supply. it provides a 16 db gain that can be reduced by adding external series resistors. the 3 db bandwidth is 4.5 ghz, and it has a differential input impedance of 160 . it has a differential output impedance of 10 and an output common-mode adjust voltage of 1.1 v to 1.8 v. 5 ? 5 ? 80 ? 500 ? 500 ? 80 ? ac ? r s ? r s 0.1f 0.1f 0.1f 0.1f + ? ? ADL5566 rl + + + + 10916-034 figure 35. basic structure the ADL5566 is composed of a dual fully differential amplifier with on-chip feedback and feed-forward resistors. the gain is fixed at 16 db but can be reduced by adding two resistors in series with the two inputs (see the gain adjustment and interfacing section). the amplifier is designed to provide a high differential open-loop gain and has an output common-mode circuit that enables the user to change the output common-mode voltage by applying a voltage to a vcomx pin. the amplifier is designed to provide superior low distortion at frequencies to and beyond 300 mhz with low noise and low power consumption. the low distortion and noise are realized with a 3.3 v power supply at 140 ma. the dual amplifier has an extremely high gain bandwidth (gbw) product that results in distortion levels that are the best in the industry for power consumed at frequencies beyond 100 mhz. this amplifier achieves greater than ?69 dbc imd3 at 500 mhz and ?100 dbc at 200 mhz for 2 v p-p operation. in addition, the ADL5566 can also deliver 5 v p-p operation under heavy loads. the internal gain is set at 16 db, and the part has a noise figure of 6.5 db and a rti of 1.5 nv/hz. when comparing noise figure and distortion performance, this amplifier delivers the best in category spurious-free dynamic range (sfdr). the ADL5566 is very flexible in terms of i/o coupling. it can be ac- or dc-coupled. for dc coupling, the output common-mode voltage (vcomx) can be adjusted (using the vcomx pin) from 1.1 v to 1.8 v output for vccx at 3.3 v and up to 3 v with vccx at 5 v. for the best distortion, the common-mode output should not go below 1.25 v at vccx equal to 3.3 v and 1.35 v for 5 v vccx operation. note that the input common-mode voltage slaves to the vcomx output voltage when ac-coupled at the inputs. for dc-coupled inputs, the input common-mode voltage should also stay between 1.25 v and 1.8 v for a 3.3 v supply and 1.35 v to 3.5 v for a 5 v supply. note again that, for ac-coupled applications with series capacitors at the inputs, as in figure 37, the output common-mode voltage, vcomx, sets the common-mode input to the same level. because of the wide input common-mode range, this part can easily be dc-coupled to many types of mixers, demodulators, and amplifiers. forcing a higher input vcomx does not affect the output vcomx in dc-coupled mode. note that, if the outputs are ac-coupled (see the adc interfacing section), no external vcomx adjust is required because the amplifier common-mode outputs are set at vccx/2.
data sheet ADL5566 rev. a | page 15 of 24 applications informa tion basic connections figure 36 shows the basic connections for operating the ADL5566 . apply a voltage between 3 v and 5 v to the vcc1 and vcc2 pin s through a 5.1 nh inductor and decouple the supply side of the inductor with at least one low inductance , 0.1 f surface - mo unt ceramic capacitor . in addition, decouple the vcom1 and vcom2 pin s (pin 21 and pin 10) using a 0.1 f capacitor. the enbl1 and enbl2 pins (pin 22 and pin 9) are tied to their amplifiers vcc_ x pin to enable each amplifier. a differential signal is applied to a mplifier 1 th r ough p in 1 ( vin1 ) and pin 2 ( vip1 ) and to a mplifier 2 through p in 5 ( vip 2 ) and pin 6 ( vin2 ) . each amplifier has a gain of 16 db. the input pins , pin 1 ( vin1 ) and pin 2 ( vip1 ) , and the output pins , p in 18 ( von1 ) and pin 17 ( vop1 ) , are biased by applying a voltage to pin 21 ( vcom1 ). if vcom1 is left open , vcom1 equal s ? of v cc1 . the input pins , pin 5 ( v ip2 ) and pin 6 ( vin2 ) , and the output pins , pin 13 ( von2 ) and pin 14 ( vop2 ) , are biased by applying a voltage to vcom2 . if vcom2 is left open , vcom2 equal s ? of vcc2 . the ADL5566 can be ac - coupled as shown in figure 36 or can be dc - coupled if within the specified input and output c ommon - mode voltage ranges ( s ee the circuit description section). to enable the ADL5566 , the enbl1 and enbl2 pin s must be pulled high. pulling the enbl1 / enbl2 pins low puts the ADL5566 in sleep mode, reducing the current co nsumption to 7 ma at ambient. a series 5 .1 nh inductor can be connected to the vcc x pins with the v cc decoupling capacitor connected to the v cc bus side ( s ee figure 53 .) this inductor with the internal capacitance of the amplifier results in a two pole low - pass network and reduces the amplifier v cc noise. balanced source ? r s ? r s 0.01 f 0.01 f balanced load vip1 vin1 0.01 f 0.01 f von1 vcom1 vop1 0.01 f vcc2 0.01f 10f vcc r f r f r g r g 2 21 18 18 18 17 1 2 1 enbl1 enbl2 vcc vcc r g 2 21 18 11 17 1 22 9 0.01f vcc1 ADL5566 5.1nh 5.1nh 20 balanced source ? r s ? r s 0.01 f 0.01 f balanced load vip2 vin2 nc nc nc nc nc nc nc nc nc nc 0.01 f 0.01 f vop2 vcom2 von2 0.01 f r f r f r g r g 5 3 4 7 8 12 15 16 19 23 10 14 13 24 6 + notes 1. exposed paddle is internally connected to gnd and must be soldered to a low impedance ground plane. exposed pad 10916-035 figure 36 . basic connections
ADL5566 data sheet rev. a | page 16 of 24 input and output interfacing the ADL5566 can be configured as a differential-input-to- differential-output driver, as shown in figure 37. the 36 resistors, r1 and r2, combined with the etc1-1-13 balun transformer, provide a 50 input match for the 160 input impedance. the input and output 0.1 f capacitors isolate the v cc /2 bias from the source and balanced load. the load should equal 200 to provide the expected ac performance (see the specifications section). etc1-1-13 v cc ? rl ? rl 0.1f 0.1f + ? ? ADL5566 a c 0.1f + 0.1f + + + 50 ? r2 r1 10916-036 figure 37. differential-input-to-differential-output configuration the differential gain of the ADL5566 is dependent on the source impedance and load, as shown in figure 38. 5 ? 5 ? 80 ? 500 ? 500 ? 80 ? ac ? r s ? r s 0.1f 0.1f 0.1f 0.1f + ? ? ADL5566 rl + + + + 10916-037 figure 38. differential input loading circuit the differential gain can be determined by l l v r r a ? ?? 1080 500 (1) single-ended input to differential output the ADL5566 can also be configured in a single-ended-input-to- differential-output driver, as shown in figure 39. in this configuration, the gain of the part is reduced due to the application of the signal to only one side of the amplifier. the input and output 0.1 f capacitors isolate the v cc /2 bias from the source and the balanced load. r2 is used to match the single-ended input impedance of the amplifier (131 ) with the 50 source. r1 is selected to balance the input of the amplifier. see application note an-0990 for more information on terminating single-ended inputs. the performance for this configuration is shown in figure 16 and figure 24. v c c ? rl ? rl 0.1f 0.1f + ? ? ADL5566 a c 0.1f 0.1f + + + + r s r2 77 ? r1 30 ? 10916-038 figure 39. single-ended-input-to-di fferential-output configuration the single-ended gain configuration of the ADL5566 is dependent on the source impedance and load, as shown in figure 40. 5 ? 5 ? 80 ? 500 ? 500 ? 80 ? ? rl ? rl 0.1f 0.1f + ? ? ADL5566 ac 0.1f 0.1f + + + + r s r2 77 ? r1 30 ? 10916-039 figure 40. single-ended input loading circuit the single-ended gain can be determined by the following two equations: 131 131 ? ? ? r2 r2 r match l l match s match s s s v1 r r r rr r2r r2 r2r r2r a ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 10 80 500 gain adjustment and interfacing the effective gain of the ADL5566 can be reduced by adding two resistors in series with the inpu ts to reduce the 16 db gain. 5 ? 5 ? 80 ? 500 ? 500 ? 80 ? ac ? r s ? r s 0.1f 0.1f 0.1f 0.1f + ? ? ADL5566 rl + + r series r series r shunt 10916-040 figure 41. gain adjustment using a series resistor show
data sheet ADL5566 rev. a | page 17 of 24 t o find r series for a given a v gain and r l , use the following: r series = 80 10 500 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + l l v r r a ( 3 ) t o calculate the a v gain for a given r series and r l , use the following: ? ? ? ? ? ? + ? ? ? ? ? ? + = l l series gain r r r a 10 80 500 (4) ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 17 18 19 20 1m 10m 100m 1g 10g frequency (hz) gain (db) 10916-041 figure 42 . sdd21 , v pos = 3.3 v , three g ains , 25 c the necessary shunt component, r shunt , to match to t he source impedance, r s , can be expressed as 160 2 1 1 1 + ? = series s shunt r r r ( 5 ) the voltage gain for multiple shunt resistor values are summarized in table 5 . the source resistance and input impedance need careful attention when using equ ation 5 . the reactance of the input impedance of the ADL5566 and the ac coupling capacitors must be considered before assuming that they make a negligible contribution. ?120 ? 1 15 ? 1 10 ?105 ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 0 50 100 150 200 250 300 350 400 450 500 frequenc y (mhz) dis t ortion (dbc) hd2 3.3v hd3 3.3v imd 3.3v hd2 5v hd3 5v imd 5v 10916-042 figure 43 . imd , hd2, and hd3 vs . frequency , a v = 6 db , 2 v p - p output, v pos = 3.3 and v pos = 5 v table 5 . differential gain adjustment using series resistor target gain (db) actual gain (db) r s (?) r series (?) 1 r shunt (?) 1 0 ?0.1 50 396.2 52.8 1 + 1.2 50 344.4 53.1 2 + 2.1 50 298.3 53.5 3 + 2.9 50 257.1 54 4 + 4.1 50 220.5 54.5 5 + 5.1 50 187.8 55.1 6 + 6.1 50 158.7 55.8 7 + 6.9 50 132.7 56.7 8 + 8.1 50 109.6 57.6 9 + 8.9 50 89 58.7 10 + 10 50 70.6 60 11 + 11.1 50 54.2 61.4 12 + 12 50 39.6 63.2 13 + 12.8 50 26.6 65.3 14 + 14 50 15 67.9 15 + 15.1 50 4.8 70.9 16 + 15.8 50 0 72.7 1 the resistor values are rounded to the nearest real resistor value.
ADL5566 data sheet rev. a | page 18 of 24 adc interfacing the ADL5566 is a dual high output linearity amplifier that is optimized for adc interfacing. one option of applying the ADL5566 to drive an adc is shown in figure 47. the wideband 1:1 transmission line balun provides a differential input to the amplifier, and the 36 resistors provide a 50 match to the source. the ADL5566 is ac-coupled from the input and output to avoid common-mode loading. a reference voltage is required to bias the ad9268 inputs and is delivered through the 200 resistors. these, in parallel with the 400 resistor, create the low frequency amplifier load of 200 . the 56 nh inductors and the 56 pf capacitor are used to create a 70 mhz low-pass filter. the two 25 resistors are added to raise the ADL5566 output impedance, which reduces peaking when the filter drives a light load. the two 25 resistors provide isolation to the switching currents of the adc sample-and-hold circuitry. the ad9268 dual adc presents a 6 k differential load impedance and requires a 1 v p-p to 2 v p-p input signal to reach full scale. the system frequency response is shown in figure 46. by applying a 2 v p-p, 32 mhz single-tone signal from the ADL5566 in a gain of 16 db, an sfdr of 94.6 dbc is achieved. by applying two half scale signals of 32 mhz and 33 mhz from the ADL5566 in a gain of 16 db, an sfdr of 90.5 dbc is realized. 0 6 0 121824303642 5460 48 amplitude (dbfs) frequency (mhz) ?15 ?30 ?45 ?60 ?75 ?90 ?105 ?120 ?135 ?150 3 + 5 6 2 10916-043 snr = 74.28db fund freq = 32.123mhz fund power = ?1.014dbfs second harm = ?94.629dbc third harm = ?95.19dbc fourth harm = ?99.98dbc fifth harm = ?104.971dbc sixth harm = ?107.105dbc 4 figure 44. measured single-tone performance of the circuit in figure 47 for a 32 mhz input signal 60 0 12 18 24 30 36 42 48 54 60 amplitude (dbfs) frequency (mhz) ?15 ?30 ?45 ?60 ?75 ?90 ?105 ?120 ?135 ?150 10916-044 fundamental1 = ?7.03dbfs fundamental2 = ?7.05dbfs imd (2f1 ? f2) = ?90.53dbc imd (2f2 + f1) = ?96.81dbc noise floor = ?114.703db figure 45. measured two-tone performance of the circuit in figure 47 for a 32 mhz and 33 mhz input signals ?20 ?19 ?18 ?17 ?16 ?15 ?14 ?13 ?12 ?11 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 0 20 40 60 80 100 120 140 160 frequency (mhz) normalized (dbfs) 10916-045 figure 46. measured relative frequency response of the wideband adc interface depicted in figure 47 vin_1 vip_1 56pf ad9268 side a etc1-1 v c c 200 ? 200 ? 0.1f 0.1f + ? ? ADL5566 ac 0.1f + 0.1f + + + 50 ? 36 ? 36 ? 400 ? 25 ? 25 ? v ref 25 ? 25 ? 16 10916-046 figure 47. wideband adc interfacing example featuring the ad9268
data sheet ADL5566 rev. a | page 19 of 24 d c -c oupled receiver a pplication the ADL5566 is well suited for dc - coupled applications, such as zero - if direct conversion receivers. an example receiver configuration is shown in figure 48 , consisting of the adl5380 quadrature demodulator and the ADL5566 dual differential amplifier. this is an ideal combination because of the wide rf input bandwidth from 400 mhz to 6 ghz, the high linearity of the ADL5566 , and when operating on a 5 v supply, le vel shifting to alig n the common - mode voltage is n o t required. the interface between the adl5380 and the ADL5566 is straight forward because the impedance presented by the ADL5566 is sufficiently high enough to permit directly connecting the two devices without any degrad ation in performance. when using the ADL5566 as shown in figure 48 , the oip3 s at the ou t puts are improved due to the high oip3 of the amplifier pair ( s ee table 6 ). in a real - world receiver where blockers are present , it is advantageous to insert a low - pass filter between the adl5380 and the ADL5566 to remove these undesired signals. if the ADL5566 is followed by an adc, insert an antialiasing filter between the ADL5566 and the adc to prevent broadband noise from aliasing back in band . for more information on this interface, see the adc interfacing section. the cascade of the performance of the circuit shown in figure 48 is presented in table 6 . loin ilo v s qlo rfin ad j 0.1f 100pf vcc1 vcc2 vcc3 g nd 2 g nd 2 g nd 4 g nd 4 gnd3 gnd1 g nd 1 gnd3 rfip 0 90 ihi loip qhi n c e nb l 0.1f 100pf 0.1f 100pf 1.5k? 100pf 100pf tc1-1-13 r4 0? 0? tc1-1-13 100pf 100pf 0.01 f balanced load vip1 vin1 0.01 f von1 vcom1 vop1 0.01 f vcc2 r f r f r g r g 2 21 18 18 18 17 1 2 1 enbl1 enbl2 vcc vcc r g 2 21 18 11 17 1 22 9 vcc1 ADL5566 20 0.01 f balanced load vip2 vin2 nc nc nc nc nc nc nc nc nc nc 0.01 f vop2 vcom2 von2 0.01 f r f r f r g r g 5 3 4 7 8 12 15 16 19 23 10 14 13 24 6 10916-052 19 24 13 6 12 4 3 23 9 10 20 16 15 18 7 22 21 1 2 5 8 11 14 17 gnd3 gnd3 0.01f 10f vcc 0.01f 5.1nh 5.1nh + figure 48 . dc - c oupled interface example featuring the adl5380 table 6 . cascade performance of t he adl5380 and ADL5566 if frequency = 200 mhz, r l = 200 ? , v out = 2 v p - p c omposite frequency (mhz) hd2 (dbc) hd3 (dbc) oip3 (dbm) adl5380 oip3 (dbm) 1 oip2 (dbm) voltage gain (db) power gain (db) 900 ?79.3 ?84.2 44.9 26.2 91.8 18.1 12.0 1900 ?82.2 ?80.5 40.8 26.5 83.9 18.1 12.0 2700 ?80.7 ?73.9 39.6 25.7 75.6 18.1 12.0 1 output referred ip3 of the adl5380 , p in = ?14 dbm, and r l = 200 ?.
ADL5566 data sheet rev. a | page 20 of 24 layout consideration s high - q inductive drives and loads, as well as stray transmission line capacitance in combination with package parasitics, can potentially form a resonant circuit at high frequencies, resulting in excessive gain peaking or possible oscillation. if rf tran smission lines connecting the input or output are used, design them such that stray capacitance at the input/output pins is minimized. in many board designs, the signal trace widths should be minimal where the driver/receiver is no more than one - eighth of the wave - length from the amplifier. this nontransmission line configuration requires that underlying and adjacent ground and low impedance planes b e dropped from the signal lines. analyzer amplifier 1 5.1nh + vin_1 vip_1 etc1-1 etc1-1 vcc 34.8 ? 0.1 f 0.1 f + ? ? ADL5566 ac 0.1 f + 0.1 f + + + 50 ? 50 ? 36 ? 36 ? 34.8 ? 84.5 ? 84.5 ? 0.1 f 10916-047 figure 49 . general - purpose characterization cir cuit + ac 50 ? port 2 port 1 port 3 port 4 ac 50 ? ac 50 ? amplifier 1 5.1nh vin_1 vip_1 vcc 0.1 f 0.1 f + ? ? ADL5566 ac 0.1 f + 0.1 f + + + 50 ? 36 ? 50 ? 50 ? 0.1 f 10916-048 figure 50 . differential characterizatio n circuit using agilent e8357a four - port pna + analyzer amplifier 1 5.1nh vin_1 vip_1 etc1-1 etc1-1 vcc 34.8 ? 0.1 f 0.1 f + ? ADL5566 ac 0.1 f + 0.1 f + + + 50 ? 50 ? 36 ? 36 ? 2k ? 2k ? 34.8 ? 84.5 ? 84.5 ? 0.1 f vcom output input common-mode v adjust 10916-049 figure 51 . disto r tion m easurement circuit for various common - m ode voltages
data sheet ADL5566 rev. a | page 21 of 24 soldering informatio n and reco mmended land patte rn figure 52 shows the recommended land pattern for the ADL5566 . the adl556 6 is contained in a 4 mm 4 mm lfcsp package, which has an exposed ground paddle (epad). this paddle is internally connected to the ground of the chip. to minimize thermal impedance and ensure electrical performance, solder the paddle to the low impedanc e ground plane on the printed circuit board ( pcb ) . to further reduce thermal impedance, it is recommended that the ground planes on all layers under the paddle be stitched together with vias. for more information on land pattern design and layout, refer to the an - 772 application note, a design and manufacturing guide for the lead frame chip scale package (lfcsp) . this land pattern, on the ADL5566 evaluation board, provides a measured thermal resistance ( ja ) of 34.0 c/w. to measure ja , the temperature at the top of the lfcsp package is found with an ir temperature gun. thermal simulation suggests a junction temperature 1.5c higher than the top of package temperature. with additional ambient temperature and i/o power measure - ments, ja c an be determined. 13 mils 39 mils 12 mils 98.4 mils 91 mils 91 mils 13.7 mils 19.7 mils 157.4 mils 10916-050 figure 52 . recommended land pattern evaluation board figure 53 shows the schema tic of the ADL5566 evaluation board. the board is powered by a single supply in the 3 v to 5 v range. the power supply is decoupled by 10 f and 0.1 f capacitors. the l1 and l2 i nductors decoupl e the ADL5566 from the power supply. table 7 details the various configuration options of the evaluation board. figure 54 and figure 55 show the component and circuit side layouts of the evaluation board. the balanced input and output interfaces are converted to single ended with a pair of baluns (m/a - com etc1 - 1 - 13). the baluns at the input, t1 and t2, provide a 50 ? sin gle - ended - to - differential transformation. the output balun s, t3 and t4 , and the matching com ponents are configured to provide a 200 to 50 impedance transformation with an insertion loss of about 11 db.
ADL5566 data sheet rev. a | page 22 of 24 1 24 enbl1 ADL5566 vcom1 vcc1 nc viin1 vip1 nc nc vip2 vin2 von1 vop1 nc nc vop2 von2 enbl2 vcom2 vcc2 23 22 21 20 19 7 8 9 10 11 12 2 3 4 5 6 18 17 16 15 14 13 exposed paddle 1 2 3 1 2 3 v pos vcom-2 v cc vcom-1 v cc v pos enbl_1 enbl_2 2 2 c11 dni dni dni r28 dni t3 t4 gnd + v cc v cc r5 0 ? r24 0 ? r21 0 ? r8 0 ? c3 0.1f c4 0.1f c6 0.1f c7 0.1f c5 0.1f l1 5.1nh c18 0.01f c17 0.01f c19 0.01f c20 0.01f c21 10f r13 84.5 ? r14 84.5 ? r16 84.5 ? r15 84.5 ? r19 34.8 ? r20 34.8 ? r18 34.8 ? r17 34.8 ? r27 dni r26 0 ? r25 0 ? c10 dni c12 dni dni 2 t1 r1 dni c14 0.01f c13 0.01f r10 36? r9 36 ? dni 2 c2 0.1f dni t2 c15 0.01f c16 0.01f r2 dni r4 0 ? r3 0 ? r12 36? r11 36? nc nc nc nc nc vin1 vip1 c1 vip2 v in2 vop1 von1 von2 vop2 l2 5.1nh 10916-051 figure 53. evaluation board schematic table 7. evaluation board configuration options component description default condition v pos , gnd ground and supply test loops. v pos , gnd = installed c5, c7, c21, l1, l2 power supply decoupling. the supply decoupling consists of a 10 f capacitor (c21) and two 0.1f capacitors, c5 and c7, connected between the supply lines and ground. l1 and l2 decouple the ADL5566 from the power supply. c21 = 10 f (size d), c5, c7 = 0.1 f (size 0402), l1, l2 = 5.1 nh (size 0603) vin1, vip1, vip2, vin2, r1, r2, r3, r4, r5, r8, r9, r10, r11, r12, r21, r24, c13, c1, c12, c14, c15, c16, t1, t2 input interface. the sma labeled vin1 is the input to amplifier 1. t1 is a 1:1 impedance ratio balun to transform a single-ended input into a balanced differential signal. removing r3, installing r1 (0 ), an d installing an sma connector (vip1) allow driving from a differential source. c13 and c14 provide ac coupling. c12 is an optional bypass capacitor. r9 and r10 provide a differential 50 input termination. the sma labeled vip2 is the input to amplifier 2. t2 is a 1:1 impedance ratio balun to transform a single-ended input into a balanced differential signal. removing r4, installing r2 (0 ), and installing an sma connector (vin2) allow driving from a differential source. c15 and c16 provide ac coupling. c1 is an optional by pass capacitor. r11 and r12 provide a differential 50 input termination. vin1, vip2 = installed, vip1, vin2 = not installed, r1, r2 = dni, r3, r4, r5, r8, r21, r24 = 0 (size 0402), r9, r10, r11, r12 = 36 (size 0402), c13, c14, c15, c16 = 0.01 f (size 0402), c1, c12 = dni, t1, t2 = etc1-1-13 (m/a-com) vop1, von1, von2, vop2, c10, c11, c17, c18, c19, c20, r13, r14, r15, r16, r17, r18, r19, r20, r25, r26, r27, r28, t3, t4 output interface. the sma labeled vop1 is the output for amplifier 1. t3 is a 1:1 impedance ratio balun used to transform a balanced differential signal to a single- ended signal. removing r25, installing r27 (0 ), and installing an sma connector (von1) allow differential loading. c10 is an optional bypass capacitor. c17 and c18 provide ac coupling. r13, r14, r17, and r16 are provided for generic placement of matching components. the sma labeled von2 is the output for amplifier 2. t4 is a 1:1 impedance ratio balun used to transform a balanced differential signal to a single-ended signal. removing r26, installing r28 (0 ), and installing an sma connector (vop2) allow differential loading. c11 is an optional bypass capacitor. c19 and c20 provide ac coupling. r15, r16, r19, and r20 are provided for generic placement of matching components. the evaluation board is configured to provide a 200 to 50 impedance transformation with an insertion loss of 11 db. vop1, von2 = installed, von1, vop2 = not installed, r13, r14, r15, r16 = 84.5 (size 0402), r17, r18, r19, r20 = 34.8 (size 0402), r25, r26 = 0 (size 0402), r27, r28 = dni (size 0402), c10, c11 = dni (size 0402), c17, c18 = 0.01 f (size 0402), c19, c20 = 0.01 f (size 0402), t3, t4 = etc1-1-13 (m/a-com)
data sheet ADL5566 rev. a | page 23 of 24 component description default condition enbl _1, enbl _2, c3, c4 device enable. enbl _ 1 is the enable for a mplifier 1. connecting a jumper between p in 2 and v pos enables a mplifier 1. c3 is a bypass capacitor. enbl _2 is the enable for a mplifier 2. connecting a jumper between p in 2 and v pos enables a mplifier 2. c4 is a bypass capacitor. enbl _ 1, enbl _ 2 = installed, c3, c4 = 0.1 f (size 0402) vcom -1, vcom - 2 , c2, c6 common - mode voltage interface. vcom1 is the common - mod e interface for a mplifier 1. a voltage applied to this pin sets the common - mode voltage of the output of a mplifier 1. vcom2 is the common - mode interface for a mplifier 2. a voltage applied to this pin sets the common - mode voltage of the output of a mplifier 2. typically decoupled to ground with a 0.1 f capacitor (c2 and c6) . with no reference applied , input and output common mode float to midsupply (v cc /2). vcom - 1, vcom - 2 = installed c2, c6 = 0.1 f (size 0402) 10916-054 figure 54 . la yout of evaluation board, component side 10916-055 figure 55 . layout of evaluation board, circuit side
ADL5566 data sheet rev. a | page 24 of 24 outline dimensions 0.50 bsc 0.50 0.40 0.30 compliant to jedec standards mo-220-wggd-8. bot t om view top view 4.10 4.00 sq 3.90 se a ting plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.203 ref coplanarity 0.08 pin 1 indic a t or 1 24 7 12 13 18 19 6 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 01-18-2012- a 0.30 0.25 0.20 pin 1 indic a t or 0.20 min 2.40 2.30 sq 2.20 exposed pa d figure 56 . 24- lead lead frame chip scale package [lfcsp_wq] 4 mm 4 mm body, ve ry very thin quad (cp - 24 - 14 ) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adl556 6 acpz - r7 ?40 c to + 85c 24- lead lead frame chip scale package [lfcsp_ w q], 7 tape and reel cp -24-14 adl556 6-e valz evaluation board 1 z = rohs compliant part . ? 2012 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10916 - 0- 12/13(a)

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